The AES16e incorporates SynchroLock clock synchronization technology to provide extreme tolerance to noisy external AES/EBU and word clock signals while generating an ultra-low jitter clock.
The SynchroLock sample clock is a two-stage system that is comprised of a fast-locking analog PLL and digitally controlled crystal-based secondary stage. Due to extensive number crunching of the secondary stage, SynchroLock typically requires one to two minutes to achieve final lock. While the secondary stage is working, the fast-locking PLL loop maintains lock, but with much less jitter attenuation than the secondary stage.
At the moment that final lock is achieved there can be an audible glitch. For this reason it is best to not record with the AES16e until final lock has been achieved.